1. Technical Field
The present invention relates to a substrate on which a semiconductor chip is mounted, and a semiconductor device using the same.
2. Related Art
In semiconductor devices, semiconductor chips having a large number of circuit elements such as transistors, resistors, capacitors and so forth formed therein are mounted typically on interconnect substrates. The circuit elements are interconnected so as to allow the semiconductor devices to exhibit circuit operations and functions required thereto. Methods of interconnecting the semiconductor chips and the interconnect substrates include the wire bonding method using gold wires, and the flip-chip bonding method connecting so as to oppose the circuit-formed surfaces with the surfaces of the interconnect substrates.
High-density mounting technologies of the semiconductor devices include a technology called SoC (system-on-chip) realizing a plurality of functions in a single system on the silicon basis, and a SiP (system-in-package) realizing a plurality of functions including those of memories, CPUs (central processing units) and so forth in a single package mounting. At present, the SiP technique attracts a public attention as a complementary technology for SoC.
In addition, PoP (package-on-package) technology has appeared as the next-generation technology coming after the SiP technology, characterized by mutually stacking packages. Major advantages of the PoP technology over the chip-stacking technology, which has currently been a mainstream of the SiP technology, reside in that production efficiency and cost are improved through improving yield ratio or facilitating tests, in that problem analysis in case of nonconformities is facilitated, in that passive components can be mounted together therewith, so that high-speed, high-density mounting can be realized, in that commercial packages are mountable, so that the technology is versatile for many applications, and in that the technology can flexibly afford various module types and geometries, and is consequently excellent in design flexibility.
A semiconductor device based on the PoP technology is composed of two or more packages, wherein the individual terminals are mutually connected by solder balls. In the base package, semiconductor chips are mounted on the interconnect substrate making use of various techniques, and thereby the semiconductor chips and the interconnect substrate are connected.
One of representative bonding techniques is such as mounting semiconductor chips onto any one of the upper or the lower surface, or onto both surfaces of the interconnect substrate through gold bumps or solder bumps, while making the circuit-formed surfaces of the semiconductor chips opposed to the interconnect substrate surfaces so as to attain flip-chip mounting, and then reinforcing the bond portion of the flip-chip bonding with an underfill resin. Another technique is such as bonding the semiconductor chips and the interconnect substrate by the wire bonding method using gold wires, and then molding them with a resin material by the potting process, the top-gate process or the printing process. Still other techniques include a technique of burying the semiconductor chips into the interconnect substrate, and a technique of disposing through-hole electrodes so as to mold entire surfaces of the bonded semiconductor chips.
The base package has lands, or bumps composed of an electro-conductive material such as solder balls, on the external terminal thereof on the lower surface of the bonding portion on the upper surface of the base package. This sort of base package is stacked and bonded with a package (also referred to as “infant package”, hereinafter) having bonding portion terminals corresponded to the bonding portion terminals formed on the upper surface of the base package. The base package is occasionally stacked with an interconnect substrate having semiconductor chips, chip-type capacitors, chip-type resistors and so forth mounted thereon. Still another case relates to the base package stacked with a relay substrate which plays a role of a spacer for the convenience of mounting of packages and so forth. The infant packages, the interconnect substrate, the relay substrate and so forth are stacked on the base package through the solder balls, a solder paste and the like, heated typically by the re-flow process, and thereby bonded.
In this sort of PoP technology, there has conventionally been concerned that warping generated in the packages may result in bonding failure between the packages. This sort of problem is ascribable to difference in the thermal expansion coefficients depending on configurations of the individual packages. Any efforts of ensuring a desirable bonding have occasionally limited the package design and materials.
Paragraphs below will described the bonding failure between the packages, referring to FIGS. 13A to 15B. These drawings are sectional views showing semiconductor devices at a temperature where solder is fused.
In the semiconductor devices shown in FIGS. 13A to 15B, and FIGS. 16A to 17B, a first interconnect substrate 203 and a second interconnect substrate 201 are stacked. The first interconnect substrate 203 is an interconnect substrate composing the base package, and the second interconnect substrate 201 is an interconnect substrate composing the infant package.
The first interconnect substrate 203 has a plurality of lands 213 provided on the surface thereof opposed to the second interconnect substrate 201. The first interconnect substrate 203 has the lands 213 arranged at the locations corresponded to the locations of the lands provided on the second interconnect substrate 201. The first interconnect substrate 203 also has a plurality of second solder balls 219 provided on the back surface opposite to the chip-mounting surface.
Also the second interconnect substrate 201 has a plurality of lands 213 provided on the surface thereof opposed to the first interconnect substrate 203. The individual lands 213 are respectively connected with first solder balls 215. The second interconnect substrate 201 is molded with a molding resin 221 on the back surface thereof opposite to the surface faced to the first interconnect substrate 203.
As shown in FIG. 13A, FIG. 14A, FIG. 15A, FIG. 16A and FIG. 16B, the first interconnect substrate 203 has a semiconductor chip 205 mounted on the surface thereof opposite to the second interconnect substrate 201. As shown in FIG. 13B, FIG. 14B, FIG. 15B, FIG. 17A and FIG. 17B, the semiconductor chip 205 is formed on the first interconnect substrate 203 specifically on the back surface thereof opposite to the surface opposed with the second interconnect substrate 201. Whichever for the case where the semiconductor chip 205 is mounted on either surface of the first interconnect substrate 203, an underfill resin 207 is provided between the semiconductor chip 205 and the first interconnect substrate 203. Conductive components (not shown) of the semiconductor chip 205 and conductive components (not shown) of the first interconnect substrate 203 are connected through bonding bumps 209.
FIG. 13A to FIG. 15B shows problems of concave warping and convex warping of the base wafer, encountered when the infant package, after being molded with a resin together with a semiconductor chip mounted thereon, is stacked on the base package having the semiconductor chip 205 mounted by flip-chip bonding onto the first interconnect substrate 203, and subjected to the re-flow process.
FIG. 13A and FIG. 13B show the first solder balls 215 on the infant package failed in making contact with the lands 213 on the base package, while leaving unconnected portion 251, in a region where a gap between the individual packages is widened due to the warping.
FIG. 14A and FIG. 14B show the first solder balls 215 collapsed and flattened in a region where a gap between the packages is narrowed due to the wrapping. The solder balls swells out from the lands 213 to contact with the substrate, no more keeping the spherical geometry, and is almost likely to produce bridged portions 253.
FIG. 15A and FIG. 15B shows the first solder balls 215 collapsed and flattened in a portion where the gap between the packages is narrowed due to the warping, forming solder ball collapsed portion 257. The solder ball collapsed portion 257 swells out from the lands 213 to contact with the substrate, deforming themselves into distorted geometry rather than sphere. FIG. 15A and FIG. 15B show the first solder balls 215 once fused and bonded but stretched to produce a cylindrical form in a region where the gap between the packages is widened, forming solder ball stretched portion 255. Formation of the solder ball stretched portion 255 and the solder ball collapsed portion 257 may also result in separation of the first solder balls 215 from the lands 213 in these portions, in the re-flow process for mounting onto mounting boards.
Conventionally known techniques of suppressing this sort of problems include those described in Japanese Laid-Open Patent Publication No. H9-8081 and Japanese Laid-Open Patent Publication No. 2004-289002.
Japanese Laid-Open Patent Publication No. H9-8081 describes a technique of making difference in the land area depending on the degree of warping of a BGA substrate.
According to Japanese Laid-Open Patent Publication No. 2004-289002, an effort is made on adjusting the height of the solder balls by varying aperture of the bonding lands used for bonding with a package. This configuration reportedly makes it possible to stack packages different in states of warping.
FIG. 16A, FIG. 16B, FIG. 17A and FIG. 17B are sectional views showing a semiconductor device corresponded to the device configuration described in this patent publication. As shown in FIG. 16A and FIG. 16B, the base package having the semiconductor chip 205 mounted on the top surface of the first interconnect substrate 203 is stacked with the second interconnect substrate 201 of the infant package after being molded with a resin together with a semiconductor chip mounted thereon. As shown in FIG. 17A and FIG. 17B, the base package having the semiconductor chip 205 mounted on the lower surface of the interconnect substrate 203 is stacked with the second interconnect substrate 201 of the infant package after being molded with a resin together with a semiconductor chip mounted thereon.
The base package shown in FIG. 16A and FIG. 16B shows concave warping. The base package shown in FIG. 17A and FIG. 17B shows convex warping. Due to the warping, the gap between the individual packages causes variation in the width by locations.
According to this patent publication, exposed area of the lands is then adjusted by providing an insulating film for adjusting aperture thereof on the lands on the interconnect substrate 203. More specifically, second lands 263 are provided in a region where the gap between the packages is widened. The second lands 263 have, formed thereon, second openings 267 having a smaller aperture than in the other region. On the other hand, first lands 261 are provided in a region where the gap between the packages is narrowed. The first lands 261 have, formed thereon, first openings 265 having a larger aperture than in the other region.
However, the above-described techniques described in Japanese Laid-Open Patent Publication No. H9-8081 and Japanese Laid-Open Patent Publication No. 2004-289002 are still remained for further improvement in bonding reliability between the substrates only with simple configurations.
For example, the exposed area of the lands in the above-described Japanese Laid-Open Patent Publication No. 2004-289002 has been adjusted by controlling the aperture of the insulating film provided on the lands, while leaving the plane geometry of the lands unchanged. It has, therefore, been anticipated that design of the insulating film is more complicated.